The goal of the course project is to mimic the research process: you will research, plan, execute, and adjust to develop a novel idea. This process involves ideation, baseline selection, design and implementation, experimentation and methodology, and presentation. The project can be related to any of the topics discussed in the class. A strong project will demonstrate understanding of topics beyond the scope of what we covered in class. The objective is to develop a work that can be eventually extended to a conference paper. Innovation is valued above all; your execution of the idea is next most important.
| Proposal | 10% |
| Weekly Progress Check-up (against proposed timeline) | 30% |
| Final Presentation | 30% |
| Final Report | 30% |
The only requirement is that the project is self-contained and realistic in scope, but not low-effort, for a 10-week quarter.
You are required to work in groups of 3.
Below is a list of project ideas. You may also propose your own unique project idea; original proposals are encouraged and may qualify for extra credit.
Modify the GeneSys systolic array to support FP16, BF16, and FP8 multiply with FP32 accumulate. INT8 multiply-accumulate is already provided; students will implement the floating-point datapaths using open-source ALU IPs (Berkeley HardFloat, PULP FPnew) as a starting point. Deliverable: RTL with testbenches passing simulation in Vivado or Verilator.
Integrate the ARA RVV 1.0 vector core with the GeneSys systolic array as a unified compute unit sharing a common memory space. GeneSys runs GEMM layers, then ARA handles the non-GEMM vector ops (softmax, RMSNorm, RoPE, SiLU, attention masking). ARA serves purely as a compute datapath — a separate control logic sits above both ARA and the systolic array to orchestrate execution. Deliverable: RTL with testbenches passing simulation in Vivado or Verilator.
Build an event-driven cycle-level simulator in C++ modeling a systolic array, vector core, and memory hierarchy. Inputs are an analytical model of components and their connectivity based on the architecture design, plus a static schedule. The simulator should predict tokens/sec and time-to-first-token (TTFT) for a given LLM configuration. Calibrate against published accelerator numbers (TPU, Gemmini, H100) within ±20%. The simulator should run a full Llama-3-8B forward pass in under 10 minutes and produce Pareto frontiers across array size, SRAM, HBM bandwidth, and vector width for both FFN-dominated and attention-dominated regimes.
Extend Astra-sim to support LLM serving workloads. Astra-sim does not natively model inference request scheduling, disaggregated prefill/decode, chunked prefill, or variable context length — students will add these capabilities. Model TP, PP, EP, and DP-attention across a cluster of abstracted accelerators. Calibrate against published vLLM/SGLang numbers. Then pick one of the following design questions to investigate: (1) TP-versus-PP crossover on 70B models, (2) disaggregated-versus-colocated goodput under realistic traces, or (3) whether Attention-FFN disaggregation (GPU+LPU) beats homogeneous GPU on tokens/sec/W for trillion-parameter MoE.
Modify the GeneSys systolic array to support two modes: systolic mode for dense GEMM (weights propagate, 2D spatial reuse) and vector mode for elementwise ops (per-lane independent execution from a shared register file). Design mode-switching logic and a shared scratchpad serving both modes. Characterize the area and performance cost of unification versus separate blocks (P1 + P2): how much does the mode-switch logic cost, and how much utilization do you recover by repurposing idle systolic MACs for vector work during softmax/RMSNorm phases? Deliverable: RTL with testbenches passing simulation in Vivado or Verilator.
Design an RTL block that accelerates four specific operations: (1) transpose via banked-memory design for conflict-free access, (2) tree reduction via segmented reduction trees for MoE combine, (3) gather for paged KV cache fetching, and (4) scatter with conflict resolution for MoE dispatch. Characterize on MoE dispatch, paged KV cache gather, and attention layout transforms, measuring what fraction of end-to-end MoE decode time the block eliminates versus a vector-core baseline. Deliverable: RTL with testbenches passing simulation in Vivado or Verilator.
The project proposal is due Sunday, 04/19/2026 at 11:59 PM PST and must be submitted as a PDF. A mandatory office hour will be held by appointment on Thursday, 04/16/2026 to go over your draft. Your proposal must address the following:
Project proposals will be graded for completion.
You are required to present your project to the class. The same guidelines that apply for the paper presentations apply for the project presentation (located on the presentation page). To restate the important guidelines, the presentation should be 35–40 minutes long, followed by a discussion/Q&A session. You should present your project as if you were presenting at a conference. However, unlike the paper presentations, you should discuss your empirical results in detail along with technical details concerning your implementation. Be prepared to show code during your presentation. Presentations will be held during the final week of class.
I will evaluate your talk on a a scale of one to ten.
| Clear Presentation of Key Ideas | 4 points |
| Clear, Well-Organized Slides | 4 points |
| Drawing High-Level Insights from Empirical Results | 1 point |
| Motivating Future Work | 1 point |
The project report should be a PDF with no more than six pages of primary content using the ISCA LaTeX template. You are allowed unlimited space for the citations and appendices, starting on page seven, but your report should be complete and understandable without reading this extra material. The project report due date is TBD.
I will evaluate your report on a a scale of one to ten. If your report is ready for submission to a conference or workshop (not in format, but in content; it should already be in the correct format), you will receive a 10% bonus to your final grade; this will be determined subjectively by me (Hadi).
| Organized Communication of Ideas | 4 points |
| Empirical Support for Proposed Technique | 3 points |
| Grammar and Spelling | 1 point |
| Clarity and Grace (i.e., clear, well organized arguments in well organized paragraphs) | 2 points |
You should demonstrate that your implementation works using both micro benchmarks and larger, potentially end-to-end, benchmarks. There are no hard requirements for the benchmarks you should use; reference the papers we have read in class for ideas or ask the TA (Hanyang Xu) if you are really stuck.
You will get a score between zero to ten based on the completeness of your implementation.